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Intel® Xeon Phi™ Coprocessor - ROADMAPS and Cluster BKMs
Attached to this thread is a PDF containing : - Guidance/communication on recent changes (and things Intel is considering) to make Cluster administration more straightforward- Calls out some tips and...
View ArticleMPICH support
Please inform if i can compile mpi code with the intel-mpi-library.Currently my host has install MPICH2 library only
View ArticleInternal error: backend signals
I'm programming on MIC recently, but I have met a disappointing problem. When I use icpc to compile my program, I find it spews an error, which is "Internal error, backend signals". Unfortunately,...
View ArticleProblem with _mm256_and_ps instruction
Hi, I was trying to do a very simple exercise using vector instructions. But I am getting wrong results. In the following program I am trying to do a bit-wise-and operation using _mm256_and_ps...
View ArticleHow to debug mic boot problem?
Since MPSS 3.2 mics does not boot reliably way, there is following error on the console: "Initramfs unpacking failed: junk in compressed archive"There are two 7120 cards on the host and boot failure...
View ArticleExplicit Vector Programming in Fortran
No longer does Moore’s Law result in higher frequencies and improved scalar application performance; instead, higher transistor counts lead to increased parallelism, both through more cores and through...
View ArticleHow to evaluate flops of MIC card?
Hi everybody,I need to count flops of a code which should be running on MIC card with the native mode. But I don’t know the correct way to evaluate the flops. I find a document from internet, and the...
View Articleopensm does not work on OFED-3.5-2-MIC: base lid 65536
The problem that I am having is on the Mellanox InfiniBand HCA side, however, the problem is with the OFED-3.5-2-MIC-beta1 branch of OFED, so I hope this is the right forum. I am trying to configure...
View ArticleReg: How to increase Data transfer speed between host and MIC
Hi,I was trying to offload some portion of my code and I set OFFLOAD_REPORT =3. The report is like this.[Offload] [HOST] [Tag 172] [CPU Time] 0.120382(seconds) [Offload] [MIC 0] [Tag 172]...
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Power Management: So what is this policy thing?
Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.I have talked...
View ArticleProblem with Scatter/Gather operations
Hi, i am vectorizing some code using the MIC intrinsics. But i am getting segmentation fault on MIC (offload error: process on the device 0 was terminated by signal 11 (SIGSEGV) ). Some one please tell...
View ArticleCalculating prefetches that missed L2
Hi, I am currently doing some performance tests on some offload code for Xeon Phi. I have been calculating performance numbers by measuring hardware counters using PAPI, with the calculation methods...
View ArticleWhich optimizations are applied in O1?
On Xeon Phi coprocessor, I have obtained 5x speedup when the following code is compiled with O1 instead of O0, for a single thread.int i; for( i = 0; i < nrows; i++){ int j; double y0 = 0.0; int...
View ArticleMemory allocated on MIC creates a copy on main memory?
Hi,I find out that main memory also stores a copy of data allocated on MIC Card when handling big data on MIC Card. For example, given below codes, the program uses 1G RAM when pausing at "Press key to...
View ArticleNew case study: shallow water equation solver
We have just published a new paper with a case study of the Intel MIC architecture.http://research.colfaxinternational.com/post/2014/05/12/Shallow-Water.aspxThis is a simplified CFD application solving...
View ArticleDebugger cache in windows
I'm having trouble debugging my offload executable in windows, and I suspect there may be a cache someplace that needs to be purged. If I create a new solution/project with the same name as my real...
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Binomial Options Pricing Model Code for Intel® Xeon Phi™ Coprocessor
IntroductionThe Binomial Options Pricing Model (BOPM) is a generalized numerical method used to value options in the quantitative Financial Services industry. To be accurate, it is a lattice-based...
View Articlewhat is the relation between "hardware thread" and "hyperthread"?
Dear Forum,One of the Intel TBB webpages states that "a typical Xeon Phi coprocessor has 60 cores, and 4 hyperthreads/core". But this blog from Intel emphasizes that "The Xeon Phi co-processor utilizes...
View ArticleSubmissions open: High Performance Parallelism Gems
You are invited to contribute to High Performance Parallelism Gems – Successful Approaches for Multicore and Many-core Programming (working title) a contribution-based book that will focus on practical...
View Articleweird error of Xeon Phi cards on running IMB
Hi,I am using Intel MPI Benchmark to evaluate my Xeon Phi cards (5110p). Particularly, for the Pingpong test, all of my cards work well but one. This card will fail and automatically reboot when the...
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