Hi,
I am trying to control the duty cycle of mic cores (through IA32_CLOCK_MODULATION), but I just found the following limited information in the Developer's Guide.
"The processor implements internal MSRs (IA32_THERM_STATUS, IA32_THERM_INTERRUPT,
IA32_CLOCK_MODULATION) that allow the processor temperature to be monitored and the processor performance to
be modulated in predefined duty cycles under software control."
How could the duty cycles be software controlled on MIC? On SandyBridge (and others) one can use MSR Inline Assembly or msr device files to achieve this.
The paragraph immediately following the above confuses me a little bit:
" The Intel® Xeon PhiTM coprocessor supports non-ACPI based thermal monitoring through a dedicated TMU and a set of
thermal sensors. Thermal throttling of the core clock occurs automatically in hardware during a thermal event.
Additionally, OS power-management software is given an opportunity to modulate the core frequency and voltage in
response to the thermal event. These core frequency and voltage settings take effect when the thermal event ends. In
other words, Intel® Xeon PhiTM coprocessor hardware provides equivalent support for handling thermal events but
through different mechanisms. "
If thermal throttlin occurs automatically in hardware, will the duty cycles still controllable in software? OS power-management software can modulate core frequency and voltage, that is DVFS, can OS power-management control the duty cycle? If not, how could "the processor performance ...under software control." ?
In short, how could we software-modulate the duty cycles on MIC?
Thank you!