Hi,
Recall Figure 2-12 (Host and Intel® MIC Architecture Physical Memory Map) on in the Intel Xeon Phi Systems Software Developers Guide.
The low memory (0 - 512G) is divided into 8x64GB blocks where block 0 is the Xeon Phi's own GDDR / MMIO space. The blocks 1-7 are referred to as "Local Resources of Other KNC". I have multiple Xeon Phis in my machine and want to access the GDDR memory of the other card directly. I assume that this should be possible by accessing this memory range.
My questions:
Assume, I have 4 cards A, B, C and D. I start two applications one A and C. I want to have these two communicate with each other. How do they know which coprocessor (0,1,2,3) they have to access i.e. how do I know that coprocessor 2 on the figure is in fact C and not B or D? Is this consistent, i.e. if I am on coprocessor 2, then the other blocks will be coprocessor 0,1,4 ? How do I know my own ID?
I hope it's clear what I mean...
Further Information: I am not using Linux / MPSS for doing that. We have developed our own OS for the host / card.
Thanks,
Reto